| fm_top Project Status | |||
| Project File: | dds_top.xise | Parser Errors: | No Errors |
| Module Name: | fm_top | Implementation State: | Synthesized |
| Target Device: | xc6slx9-2tqg144 |
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No Errors |
| Product Version: | ISE 13.2 |
|
48 Warnings (0 new) |
| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slice Registers | 169 | 11440 | 1% | |
| Number of Slice LUTs | 88 | 5720 | 1% | |
| Number of fully used LUT-FF pairs | 61 | 196 | 31% | |
| Number of bonded IOBs | 25 | 102 | 24% | |
| Number of Block RAM/FIFO | 1 | 32 | 3% | |
| Number of BUFG/BUFGCTRLs | 1 | 16 | 6% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | 周日 五月 6 20:19:43 2012 | 0 | 48 Warnings (0 new) | 9 Infos (0 new) | |
| Translation Report | Out of Date | 周四 九月 29 15:25:19 2011 | 0 | 25 Warnings (25 new) | 0 | |
| Map Report | Out of Date | 周四 九月 29 15:27:40 2011 | 0 | 1 Warning (1 new) | 9 Infos (9 new) | |
| Place and Route Report | Out of Date | 周四 九月 29 15:27:49 2011 | 0 | 0 | 2 Infos (2 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Out of Date | 周四 九月 29 15:27:54 2011 | 0 | 0 | 2 Infos (2 new) | |
| Bitgen Report | Out of Date | 周四 九月 29 15:28:04 2011 | 0 | 1 Warning (1 new) | 0 | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| WebTalk Report | Out of Date | 周四 九月 29 15:28:04 2011 | |
| WebTalk Log File | Out of Date | 周四 九月 29 15:28:05 2011 | |